1. Field of the Invention
The present invention relates to an operation analysis apparatus for analyzing the operation of an arbitration circuit for arbitrating access to a memory, a method for analyzing the operations thereof, and a computer program product that contains a computer-readable program for executing the method.
2. Description of the Related Art
Controllers employed in image forming apparatuses, PCs, or the like have a circuit configuration in which a plurality of interfaces (I/Fs) are connected to one bus. This type of controller allows only one I/F to have a bus use right at a moment and prevents a plurality of I/Fs from using the bus simultaneously. In order to arbitrate the use of the bus by a plurality of I/Fs, the controller includes an arbiter as an arbitration circuit.
The arbiter determines the degree of priority for using the bus, provides one of the I/Fs with a right of use in accordance with the degree of priority, and allows the I/F to access the bus. An I/F that is assigned a low degree of priority, therefore, gains little improvement in system performance by I/F speedup when access requests from the I/Fs conflict.
In view of the above, an arbiter has been developed that is provided with a function of switching the degree of priority to allow even an I/F with a low degree of priority to ensure performance.
In order to check this function, however, the I/Fs are required to be operated simultaneously. Under circumstances where the circuit scale has increased and functions of I/Fs have become complicated in recent years, it has become difficult to perform the checking easily.
With this being the situation, a controller has been developed that can check the operation of an arbiter easily without operating the I/Fs (see Japanese Patent Application Laid-open No. 2004-334774). This controller is a device in which a plurality of direct memory access (DMA) circuits access a common memory, and includes interface circuits to which respective DMA circuits are connected, an arbitration circuit that arbitrates an access request from each DMA circuit, and a control circuit that starts up the DMA circuits simultaneously and checks the operation of the arbitration circuit by bypassing the interface circuits.
Although the adoption of the controller described in Japanese Patent Application Laid-open No. 2004-334774 can perform the operation checking of the arbiter, this operation checking is the checking of the degree of priority without consideration of the operation of each I/F.
In addition, it cannot be checked whether the degree of priority of the arbiter is switched as the designer intends during actual operation. When unintentional performance problems or malfunction occur, it is hard to analyze what the problem is.
Given these circumstances, there is needed to provide an apparatus and method that can record the order of priority of an arbiter in operation in a bus to which a plurality of I/Fs are connected and analyze the operation thereof, and in particular, an apparatus and method that records in what order a plurality of image processing units in an image forming apparatus access a memory, thereby allowing the way the arbiter operates to be analyzed.